//////////////////////////////////////////////////////////////////////
////                                                              ////
////  CFByteMode.v                                                ////
////                                                              ////
////                                                              ////
////  This file is part of the "Pico E12" project                 ////
////  http://www.picocomputing.com                                ////
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////                                                              ////
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//// Copyright (C) 2005, Picocomputing, Inc.                      ////
//// http://www.picocomputing.com/                                ////
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////////////////////////////////////////////////////////////////////JF

//This module detects and debounces 8 bit read and write detection
//The minimum skew between CE1 and CE2 must be 5nS
//This module can delay ByteMode by up to 10nS
`timescale 10ns / 1ns
module CFByteMode(CFClock, CE1, CE2, ByteMode);

input CFClock;                                                           
input CE1;
input CE2;
output ByteMode;

wire RawByteMode;
wire RawWordMode;

reg ByteMode;
reg ByteModeDelay;

//There is a small amount of skew between CE1 and CE2, without debouncing this will case ByteMode to go high. When
//byte mode goes high inappropirately, pre-emptive address decoding will fail.

assign RawByteMode = (CE1) ^ (CE2);                                     //High or Low bytes active, but not both
assign RawWordMode = (~CE1) && (~CE2);                                  //High and Low bytes active

always @(posedge CFClock) begin
	if (RawWordMode) begin                                               //Reset the shift register on detection of a word access
		ByteMode <= 0;
		ByteModeDelay <= 0;
	end
else						  
	if (RawByteMode) begin                                               //RawByteMode will be asserted during setup for a word read
		ByteMode <= ByteModeDelay;                                        //The signal is delayed using a shift register to prevent false positives
		ByteModeDelay <= RawByteMode;
	end
end

endmodule
